Automated GNU Makefile
PROGNAME: the name of the executable to be built
CC: the C compiler
CPP: the C++ compiler
ASM: the assambler
LD: the linker
This searches for all *.c, *.cpp and *.s files and compiles them into objects. It then links all the files into a single executable.
The strip rule is used to strip all unwanted symbols from the resulting executable. This usually results in a significant (think 40%) size optimisation.
1 2 $(VERBOSE).SILENT: 3 4 PROGNAME = prog 5 6 CC = gcc 7 CC += -c 8 CPP = g++ 9 CPP += -c 10 ASM = nasm 11 ASM += -f elf -d ELF_TYPE 12 LD = g++ 13 14 OBJFILES = $(patsubst %.c,%.o,$(wildcard *.c)) 15 OBJFILES += $(patsubst %.s,%.o,$(wildcard *.s)) 16 OBJFILES += $(patsubst %.cpp,%.o,$(wildcard *.cpp)) 17 18 all: $(PROGNAME) 19 20 clean: 21 @echo "Cleaning object files" 22 @echo " rm -f *.o" 23 rm -f *.o 24 @echo "Cleaning backups" 25 @echo " rm -f *~" 26 rm -f *~ 27 @echo "Removing programme" 28 @echo " rm -f "$(PROGNAME) 29 rm -f $(PROGNAME) 30 31 %.o: %.s 32 @echo "Assambling "$@ 33 @echo " ASM "$< 34 $(ASM) $< 35 36 %.o: %.c 37 @echo "Compiling "$@ 38 @echo " CC "$< 39 $(CC) $< 40 41 %.o: %.cpp 42 @echo "Compiling "$@ 43 @echo " CPP "$< 44 $(CPP) $< 45 46 $(PROGNAME): $(OBJFILES) 47 @echo "Linking "$@ 48 @echo " LD -o "$(PROGNAME)" "$(OBJFILES) 49 $(LD) -o $(PROGNAME) $(OBJFILES) 50 51 strip: $(PROGNAME) 52 @echo "Stripping "$(PROGNAME) 53 echo -n "Size of "$(PROGNAME)" before strip is " 54 ls -sh $(PROGNAME) | cut -d' ' -f1 55 @echo " strip "$(PROGNAME) 56 strip $(PROGNAME) 57 echo -n "Size of "$(PROGNAME)" after strip is " 58 ls -sh $(PROGNAME) | cut -d' ' -f1 59 60 nothing: 61 @echo "Nothing to do; quitting :(" 62 @echo "HINT: Try make all" 63